Path computation delay timer in multi-protocol label switched networks
US9660860B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2014 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/0659
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In general, techniques are described for a path computation delay timer for multi-protocol label switched networks. As an example, an ingress network device configured to act as an ingress for a label switched path (LSP) may perform the techniques. The ingress network device comprises an interface and a processor. The interface may receive a message indicating an error along the LSP. The processor may delay an operation performed to configure a replacement LSP to be used in place of the LSP in order to provide time during which a cause of the error along the LSP is able to be determined. When the cause of the error is determined to be a failure of a network device supporting operation of the LSP, the processor may further perform the operation to configure the replacement LSP with the ingress network device such that the replacement LSP avoids the failed network device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.