Method for providing an on-chip variation determination and integrated circuit utilizing the same
US9664737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2015 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Jul 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for providing an on-chip variation determination and an integrated circuit utilizing the same are provided. The method includes: outputting, by a launch register circuit, a test data to the capture register circuit according to the first clock; receiving, by a capture register circuit, the test data from the launch register circuit according to the second clock; adjusting, by a control circuit, a first number of a first chain of delay elements to generate the first clock and a second number of a second chain of delay elements for the capture register circuit to just capture the test data to generate the second clock; and determining, by the control circuit, a path delay between the launch register circuit and the capture register circuit based on the first number of the first chain of delay elements and the second number of the second chain of delay elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.