Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states
US9665144B2 · kind B2 · utility
1Cited by
1References
16Claims
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Key dates
| Filing date | Dec 21, 2011 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Feb 28, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.