Devices and methods for minimizing input capacitance in computer design
US9665147B1 · kind B1 · utility
0Cited by
5References
19Claims
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Key dates
| Filing date | Dec 9, 2014 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Apr 9, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In some implementations, a computing device may include a plurality of voltage regulators including a first voltage regulator and a second voltage regulator, and a multi-phase oscillator, connected to the first voltage regulator and the second voltage regulator, configured to synchronize the first voltage regulator and the second voltage regulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.