Patent · US Active

Selecting a low power state based on cache flush latency determination

US9665153B2 · kind B2 · utility

1Cited by

25References

17Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sundar Ramani · Bengaluru, IN
Arvind Raman · Alamitos, US
Arvind Mandhani · San Francisco, US
Ashish V. Choubal · Austin, US
Kalyan Muthukumar · Bengaluru, IN
Ajaya V. Durg · Austin, US
Samudyatha Chakki · Austin, US

Key dates

Filing date	Mar 21, 2014
Grant date	May 30, 2017
Priority date	—
Expiry date	Jul 28, 2035

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D30/50
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.