Method and circuit for parasitic capacitance cancellation for self capacitance sensing
US9665215B2 · kind B2 · utility
4Cited by
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30Claims
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Key dates
| Filing date | Mar 29, 2013 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Nov 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0446
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods to measure capacitance changes for a touch-sensitive capacitive matrix are described. Charge-removal circuits and measurement techniques may be employed to cancel deleterious effects of parasitic capacitances in the touch-sensitive capacitive matrix. Capacitively switching a supply during timed charge removal may be used to cancel unwanted effects due to clock jitter. The apparatus and methods can improve signal-to-noise characteristics, sensitivity, and/or dynamic range for capacitive measurements relating to touch-sensitive capacitive devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.