End-to-end error detection and correction
US9665423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2015 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Aug 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.