Method and apparatus for bit-interleaving
US9665483B2 · kind B2 · utility
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2References
8Claims
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Key dates
| Filing date | Sep 30, 2013 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Jan 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/63
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A manner of processing data for transmission in a data communication network. A node having a main memory and an interleaver is provided. Received data is stored in the main memory and a bandwidth map is prepared. The data is then selectively read out and pre-processed according to the bandwidth map and stored in an interleaver memory. The data is later read out and post-processed before interleaving into a downstream data frame. The pre- and post-processing provide the data in a more efficient form for interleaving.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.