Increased cache performance with multi-level queues of complete tracks
US9665493B2 · kind B2 · utility
14Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2014 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Oct 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/45
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary method, system, and computer program product embodiments for increased cache performance using multi-level queues by a processor device. The method includes distributing to each one of a plurality of central processing units (CPUs) workload operations for creating complete tracks from partial tracks, creating sub-queues of the complete tracks for distributing to each one of the CPUs, and creating demote scan tasks based on workload of the CPUs. Additional system and computer program product embodiments are disclosed and provide related advantages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.