Semiconductor memory device including power decoupling capacitor
US9666262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2013 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Mar 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.