Patent · US Active

DIMM SSD SoC DRAM byte lane skewing

US9666263B2 · kind B2 · utility

2Cited by
6References
16Claims
0Family size

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Key dates

Filing dateDec 17, 2015
Grant dateMay 30, 2017
Priority date—
Expiry dateDec 17, 2035

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C16/32
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A Dual In-Line Memory Module (DIMM) Solid State Drive (SSD) System-on-a-Chip (SoC) (345) is disclosed. The DIMM SSD SoC (345) can interoperate with a host memory controller (335) as though it were a traditional Dynamic Random Access Memory (DRAM) DIMM (105, 130) with system interconnect skew and on-DIMM skew, even though the DIMM SSD SoC (345) does not have on-DIMM skew. The DIMM SSD SoC (345) can include variable delay elements (422, 424, 426, 428, 430, 432, 434, 436, 438) that can replicate the delay a traditional DRAM DIMM (105, 130) experiences and that the host memory controller (335) expects, or a superior delay that minimizes system signal integrity issues, thereby increasing maximum system speed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.