Semiconductor device including cell region stacked on peripheral region and method of fabricating the same
US9666289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Feb 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are semiconductor devices including a peripheral region and a cell region stacked thereon and a method of fabricating the same. The semiconductor device may include a peripheral region including a lower substrate and a peripheral circuit provided thereon and a cell region including an upper substrate and a cell array provided thereon. The cell region may be stacked on the peripheral region. When an operation signal is applied to the cell region from the peripheral region, at least a portion of the peripheral and cell regions may be used as a ground pattern applied with a ground signal, thereby being in an electrical ground state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.