Isolation method for a stand alone high voltage laterally-diffused metal-oxide semiconductor (LDMOS) transistor
US9666511B2 · kind B2 · utility
1Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2015 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Mar 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package having a lead frame over which a first device and a second device are spaced is provided. The lead frame includes a die pad upon which a first chip and a second chip are spaced and bonded. The first chip includes the first device, which has a first operating voltage. The second chip includes the second device, which has a second operating voltage greater than the first operating voltage. A dielectric layer is arranged between the die pad and the second device. A method for manufacturing the semiconductor package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.