Patent · US Active

3D integrated circuit

US9666562B2 · kind B2 · utility

7Cited by

2References

33Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Oscar Ming Kin Law · San Diego, US
Chunchen Liu · Beijing, CN
Ju-Yi Lu · Tainan, TW

Key dates

Filing date	Jan 15, 2015
Grant date	May 30, 2017
Priority date	—
Expiry date	Jan 15, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A three-dimensional integrated circuit (3D-IC) architecture incorporates multiple layers, each layer including at least one die and at least one switch to connect the dies on the different layers. In some aspects, a power distribution network (PDN) is routed from a first layer through the switches to supply power to at least one other layer, thereby reducing routing congestion on the layers. The switches can be placed around the periphery of an IC package to improve heat dissipation (e.g., by improving heat transfer from the center to the edge of the IC package). The switches can be used for routing test signals and/or other signals between layers, thereby improving test functionality and/or fault recovery.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.