CMOS compatible memory cells
US9666586B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Aug 14, 2014 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Nov 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell and a process for production thereof, the memory cell having a CMOS substrate having two adjacent wells of opposite conductivity types, having trench isolation between the wells, wherein one of the wells is connected to a ground voltage level and the other one to a constant voltage level; a shallow lightly doped n layer in a first one of the wells; a shallow lightly doped p layer in a second one of the wells; at least a first and second deep heavily doped p regions in the first well; at least a first and second deep heavily doped n regions in the second well; and a conductor to connect the first and second deep p regions, the shallow n region, the first and second deep n regions and the shallow p region to the same input voltage level relative to the ground voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.