Semiconductor memory device
US9666597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Mar 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; a charge storage layer; a first conductor; a second conductor; and a third conductor. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends along a stacking direction of the stacked body. The first conductor is provided in the stacked body. The first conductor is in contact with the substrate. The second conductor includes a different material from the first conductor. The second conductor is in contact with a first portion of the first conductor. The third conductor includes a same material as the second conductor. The third conductor is in contact with a second portion of the first conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.