Transistor with a low-k sidewall spacer and method of making same
US9666679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.