Hardware delay compensation in digital phase locked loop
US9667237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Mar 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.