Hierarchical packing of syntax elements
US9667962B2 · kind B2 · utility
1Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2014 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Jan 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.