Apparatus and method for a voltage regulator with improved power supply reduction ratio (PSRR) with reduced parasitic capacitance on bias signal lines
US9671801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2013 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Nov 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.