Safety level specific error response scheme for mixed criticality systems
US9672095B2 · kind B2 · utility
4Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Oct 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error response method for a mixed criticality system includes assigning a safety level to an application executed by a processor. Executing the application includes a transaction between the processor and a resource. The safety level is stored at the resource. The safety level and a fault indication are transmitted from the resource to a fault collection and control unit (FCCU). The fault indication is responsive to a fault from the resource. The FCCU responds to the fault indication with an action determined by the safety level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.