Architecture for implementing erasure coding
US9672106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2014 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Jun 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing erasure coding, including identifying a plurality of storage units, determining a number of storage unit failures to be tolerated, organizing data within the plurality of storage units as a matrix of rows and columns for computing one or more parity data, configuring the matrix to include one or more additional rows having preset values, computing the one or more parity data from the matrix that corresponds to the number of storage unit failures to be tolerated, wherein the one or more parity data comprises a row parity, a first diagonal parity, and a second diagonal parity, wherein the one or more additional rows having the preset values are used to compute the first diagonal parity and the second diagonal parity; and wherein the first diagonal parity comprises a different slope from the second diagonal parity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.