CMOS gate driving circuit
US9672784B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Sep 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/023
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a CMOS gate driving circuit, comprising a plurality of shift register units which are cascade connected, and the shift register unit of the nth stage comprises: a forward-backward scan module, a latch module (200) electrically coupled to the forward-backward scan module and an output module (400) electrically coupled to the latch module; the forward-backward scan module comprises: a first module (100) and a second module (300), and the first module (100) is a transmission module in forward scan and a pull-down module in backward scan; the second module (300) is a pull-down module in forward scan and a transmission module in backward scan; both the first module (100) and the second module (300) comprise a NAND gate, which can achieve forward-backward scan for ensuring the stability of the GOA function and the smooth output of the scan voltage signal to raise the stage transfer efficiency and to effectively reduce the sequence delay of the stage transfer; meanwhile, the multiple functions of the circuit module can be achieved, and the frame width of the screen can be decreased and the power consumption can be lowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.