Optimize data protection layouts based on distributed flash wear leveling
US9672905B1 · kind B1 · utility
26Cited by
57References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Oct 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for storing data in a storage system having solid-state memory is provided. The method includes determining portions of the solid-state memory that have a faster access rate and portions of the solid-state memory that have a slower access rate, relative to each other or to a threshold. The method includes writing data bits of erasure coded data to the portions of the solid-state memory having the faster access rate, and writing one or more parity bits of the erasure coded data to the portions of the solid-state memory having the slower access rate. A storage system is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.