Efficient fabrication of BiCMOS devices
US9673191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Mar 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/60
Abstract
A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and a spacer clear region defined by an opening in a common spacer layer over the CMOS region and the bipolar region, wherein a sub-collector, a selectively implanted collector, and a base of the PNP bipolar device are formed in the spacer clear region. The PNP bipolar device further includes a collector sinker adjacent to the spacer clear region and electrically connected to the sub-collector of the PNP bipolar device. The BiCMOS device can further include an NPN bipolar device having a sub-collector, a selectively implanted collector and a base in another spacer clear region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.