Array substrate, display panel and method for manufacturing array substrate
US9673233B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 25, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | May 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136295
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate is disclosed, which includes a connection structure of a second short-circuit ring and one corresponding data line, and this connection structure includes: a first electrode disposed on a base substrate; a connection line disposed on the first electrode; a first insulating layer disposed on the first electrode and the connection line, in which the data line connected with the second short-circuit ring is disposed on the first insulating layer; a second insulating layer disposed on the data line connected with the second short-circuit ring; and a second electrode disposed on the second insulating layer, in which the second electrode is connected with the data line connected with the second short-circuit ring through a first via hole and connected with the first electrode through a second via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.