Method of preventing drain and read disturbances in non-volatile memory device
US9673278B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Aug 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A source-drain structure and method of manufacturing the same are disclosed. The source-drain structure includes a substrate containing a drain region and a source region. The drain region includes a lightly-doped ultra-shallow junction and a heavily-doped region, and a drain-substrate junction disposed in the vicinity of a junction between a side portion and a bottom portion of the lightly-doped ultra-shallow junction and the substrate, a plurality of impurity ions in the drain-substrate junction and a plurality of impurity ions in the lightly-doped ultra-shallow junction are opposite-conductivity type ions. The drain-substrate junction can smooth out the steep surface of the lightly-doped ultra-shallow junction to minimize the maximum electric field and reduce the ion flow close to the channel, and effectively reduce the inter-band tunneling hot electron effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.