Power semiconductor transistor with improved gate charge
US9673319B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 10, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Mar 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/307
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.