P-Si TFT and method for fabricating the same, array substrate and method for fabricating the same, and display device
US9673333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Feb 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
Abstract
A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.