Power multiplexing with flip-flops
US9673787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Nov 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3562
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.