Input buffer with selectable hysteresis and speed
US9673788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Aug 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. An enabling element selectively enables the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled. The first buffer stage has hysteresis feedback paths from the output node for providing hysteresis in the buffer response. The hysteresis is smaller when the first and second buffer stages are both enabled than when only the first buffer stage is enabled. The response of the second buffer stage to the input signal, when enabled, is faster than the first buffer stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.