Error correction on demand
US9673934B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Sep 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.