Multi-protocols and multi-data rates communications
US9673963B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Apr 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus for regenerating a data signal and a clock signal are provided. One of the apparatuses include clock regeneration loop circuitry configured to receive an input data signal transmitted without a reference clock signal, and to generate an output reference clock signal having an adjustable clock frequency that substantially matches a data rate of the input data signal; data detection loop circuitry configured to generate a phase offset control signal for adjusting a phase of a clock signal that samples the input data signal, and to generate, based on the phase offset control signal, a sampled input data signal; and an elastic buffer configured to generate, based on the output reference clock signal and the sampled input data signal, an output data signal that substantially aligns with the output reference clock signal, and enable the different adaptation dynamic of the loops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.