4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases
US9674025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2014 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Jul 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/01
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A four-level pulse amplitude modulation transmitter and corresponding method are provided. The transmitter includes a most significant bit processing section and a least significant bit processing section. The transmitter further includes at least one termination resistor connected to respective outputs of the processing sections to provide a transmitter output. Each of the processing sections include a set of retiming latches arranged in a parallel for aligning input parallel data and providing parallel aligned latched outputs responsive to one phase of a quarter-rate four-phase quadrature clock. Each of the processing sections further includes a serializer for serializing the parallel aligned latched outputs to provide a serialized output using quarter-rates of the quarter-rate four-phase quadrature clock. Each of the processing sections also include an output driver for driving the serialized output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.