Memory array to generate a data eye diagram
US9674062B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Dec 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a memory array to generate a data eye diagram. The memory array includes a plurality of rows of memory cells. The memory cells include a first row corresponding to a first sampling circuit of a first plurality of sampling circuits. The first sampling circuit is configured to compare an input voltage signal to a first reference voltage. The memory cells also include a second row corresponding to a second sampling circuit of the first plurality of sampling circuits. The second sampling circuit is configured to compare the input voltage signal to a second reference voltage. Each memory cell of the memory array is an incremental multi-bit counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.