Circuit techniques for efficient scan hold path design
US9678154B2 · kind B2 · utility
3Cited by
8References
36Claims
0Family size
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Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Sep 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.