Vector instructions to enable efficient synchronization and parallel reduction operations
US9678750B2 · kind B2 · utility
3Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/4074
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.