Synchronizing a translation lookaside buffer with an extended paging table
US9678890B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Sep 28, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Nov 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.