Volatile memory erasure by the randomization of data stored in memory cells
US9679632B2 · kind B2 · utility
6Cited by
1References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Apr 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.