Fabrication and design methods using selective etching and dual-material self-aligned multiple patterning processes to reduce the cut-hole patterning yield loss
US9679771B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 7, 2016 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Mar 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Design and fabrication methods to reduce the effect of edge-placement errors in the cut-hole patterning process are invented using selective etching and dual-material self-aligned multiple patterning processes. The invented methods consist of a series of processing steps to decompose the original cut-hole mask into multiple separate masks, pattern the cut holes on the resist to expose certain targeted lines, and selectively etch the exposed targeted lines (formed by dual-material self-aligned multiple patterning processes) without attacking the non-target lines. This invention provides production-worthy methods for the semiconductor industry to continue IC scaling down to sub-10 nm half pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.