Array substrate for display device and manufacturing method thereof
US9679825B2 · kind B2 · utility
1Cited by
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16Claims
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Key dates
| Filing date | Apr 17, 2015 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | May 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0312
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed between a source/drain metal pattern and a passivation layer located above the source/drain metal pattern, which are formed in a passivation hole area of a non-active area of the array substrate. Accordingly, it may be possible to prevent display failure caused by a delamination phenomenon or peel-off of a material of the passivation layer due to the lack of adhesion strength between a metal layer and the passivation layer in the passivation hole area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.