Method of manufacturing a dual-gate FinFET
US9680023B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2016 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Aug 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A method of manufacturing a dual-gate FinFET is provided. The method includes: forming a fin structure on the semiconductor substrate, depositing an oxide layer and planarizing until the top of the fin structure is exposed, depositing a hard mask layer and patterning, preforming a first etch back process to one side of the oxide layer, and then removing the rest of the hard mask layer, preforming a second etch back process to the oxide layers at both sides of the fin structure simultaneously, forming a gate dielectric layer on surface of the fin structure, then depositing gate material on the gate dielectric layer and patterning, removing gate material on top of the fin structure, forming a drive gate and a control gate at two sides of the fin structure respectively; wherein height of the control gate is higher than height of the drive gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.