Background calibration of interleaved timing errors in digital to analog converters
US9680490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2016 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Aug 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/11
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.