Dynamically controlling power management of an on-die memory of a processor
US9684360B2 · kind B2 · utility
5Cited by
23References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Apr 12, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.