Dynamically adjusting read data return sizes based on memory interface bus utilization
US9684461B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2016 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system comprises memory devices coupled to a memory controller via a memory interface bus, the memory controller for receiving one or more memory requests via an interconnect. The memory controller tracks utilization of the memory interface bus for reads from the memory devices for a selection of the one or more memory requests during a time window. The memory controller, responsive to detecting utilization of the memory interface bus for reads during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of data to be accessed from the memory devices by at least one read operation, the reduced data size selected from among at least two read data size options for the at least one read operation of a maximum read data size and the reduced read data size that is less than the maximum read data size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.