Data storage device and flash memory control method
US9684568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2014 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Mar 19, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device and a flash memory control method with high erasing efficiency are disclosed. A microcontroller is configured to maintain a plurality of logical-to-physical address mapping tables and a link table on a flash memory to record mapping information between a host and the flash memory. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. When erasing user data of logical addresses corresponding to N logical-to-physical address mapping tables, the microcontroller is configured to invalidate N entries corresponding to the N logical-to-physical address mapping tables in the link table, where N is an integer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.