Verification of system assertions in simulation
US9684744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2015 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Oct 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for design verification includes receiving a definition of a design of an integrated circuit device and at least one assertion of a property that is to be verified over the design. The definition is compiled into a graph of processing elements, including first processing elements that simulate operation of the device and at least one second processing element representing the at least one assertion. The at least one second processing element includes a hierarchical arrangement of at least one operator node and one or more leaf nodes corresponding to inputs of the at least one assertion. A simulation of the design is executed by triggering the processing elements in the graph in multiple, consecutive clock cycles and evaluating the property during execution of the simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.