Pipeline depth exploration in a register transfer level design description of an electronic circuit

US9684749B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Maarten J. Boersma · Holzgerlingen, DE
• Thomas Fuchs · Bietigheim-Bissingen, DE
• David Lang · Lörrach, DE
• Friedrich Schroeder · Stuttgart, DE

Key dates

• Filing date: Jan 23, 2015
• Grant date: Jun 20, 2017
• Expiry date: Aug 8, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/30
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any register in the output connection paths with a wire unless the register is a listed output register. An initial total cycle time value for the modified circuit design is determined. A gate level description for the modified circuit design is obtained by a macro synthesis with the initial total cycle time value. The total cycle time value for the modified circuit design is then varied in order to determine the theoretical limit of the modified circuit design. This theoretical limit is realized when negative slacks are present in a macro synthesis of the modified circuit design for a given total cycle time value. Based on this theoretical limit, the minimum pipeline depth of the circuit design is determined.