Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design
US9684756B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2016 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Jan 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Nets are assigned to wiring planes for generating a chip design. A computer is caused to execute a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.