High-voltage transistor device and production method
US9685437B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2012 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Aug 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The high-voltage transistor device has a p-type semiconductor substrate that is furnished with a p-type epitaxial layer. A well and a body region are located in the epitaxial layer. A source region is arranged in the body region, and a drain region is arranged in the well. A channel region is located in the body region between the well and the source region. A gate electrode is arranged above the channel region. In the part of the semiconductor substrate and the epitaxial layer underneath the source region and the channel region, a deep body region is present, which has a higher dopant concentration in comparison to the remainder of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.